Three chip lines under Ziwei
Chery's Ziwei chip family covers three lines: the C-series central computing chip, the S-series automotive-grade silicon carbide chip and the M-series automotive-grade control chip. Chery describes the Ziwei chips as building an independently controllable chip system.
The C100 central compute chip is designed for physical AI deployment at the edge and is deeply adapted to CheryMind.
Ziwei C100 compute and memory
With two chips, the Ziwei C100 reaches 1000KDMIPS of CPU compute, which Chery says is close to a single mid-range server CPU. Two chips also provide 2400TOPS of vehicle NPU compute, supporting deployment of 100B-parameter models, and memory bandwidth is 600GB/s.
The C100 uses a multi-core heterogeneous architecture combining CPU, NPU and VDSP with a unified memory architecture. Chery says the chip is tailored for 100B physical-world models and achieves an 80ms end-to-end algorithm loop.
Against industry benchmarks, Chery cites bandwidth roughly 2.2 times higher, compute roughly 1.2 times higher and image processing roughly 1.5 times higher.
Ziwei C100 safety certification
The Ziwei C100 carries AEC-Q100 automotive qualification. Its safety level is ASIL-B across the full chip, with an ASIL-D safety island at Grade 2.
Ziwei S1500 SiC specifications
The Ziwei S1500 silicon carbide chip has a 1500V drain-source voltage rating, which Chery describes as the industry's highest automotive-grade voltage class. Its module current capability is 1450A and its specific on-resistance Rsp is 2.0mΩ·cm².